Intel IA-32 - Manual (Page 343)

Vol. 3A 8-19
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.5.3 Error Handling
The local APIC provides an error status register (ESR) that it uses to record errors that it detects
when handling interrupts (see Figure 8-9). An APIC error interrupt is generated when the local
APIC sets one of the error bits in the ESR. The LVT error register allows selection of the inter-
rupt vector to be delivered to the processor core when APIC error is detected. The LVT error
register also provides a means of masking an APIC error interrupt.
The functions of the ESR are listed in Table 8-2.
Table 8-2. ESR Flags
FLAG Function
Send Checksum Error (P6 family and Pentium processors only) Set when the local APIC detects
a checksum error for a message that it sent on the APIC bus.
Receive Checksum Error (P6 family and Pentium processors only) Set when the local APIC detects
a checksum error for a message that it received on the APIC bus.
Send Accept Error (P6 family and Pentium processors only) Set when the local APIC detects
that a message it sent was not accepted by any APIC on the APIC bus.
Receive Accept Error (P6 family and Pentium processors only) Set when the local APIC detects
that the message it received was not accepted by any APIC on the APIC
bus, including itself.
Send Illegal Vector Set when the local APIC detects an illegal vector in the message that it is
sending.
Receive Illegal Vector Set when the local APIC detects an illegal vector in the message it
received, including an illegal vector code in the local vector table
interrupts or in a self-interrupt.
Illegal Reg. Address (Pentium 4, Intel Xeon, and P6 family processors only) Set when the
processor is trying to access a register that is not implemented in the
processors’ local APIC register address space; that is, within the address
range of the APIC register base address (specified in the
IA32_APIC_BASE MSR) plus 4K Bytes.