Intel IA-32 - Manual (Page 283)

Vol. 3A 7-15
MULTIPLE-PROCESSOR MANAGEMENT
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When an instruction is executed that enables or disables paging (that is, changes the PG
flag in control register CR0), the instruction should be followed by a jump instruction. The
target instruction of the jump instruction is fetched with the new setting of the PG flag (that
is, paging is enabled or disabled), but the jump instruction itself is fetched with the
previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the
jump operation following the move to register CR0 (because any use of the MOV
instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is
completely serializing). However, to maintain backwards and forward compatibility with
code written to run on other IA-32 processors, it is recommended that the jump operation
be performed.
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Whenever an instruction is executed to change the contents of CR3 while paging is
enabled, the next instruction is fetched using the translation tables that correspond to the
new value of CR3. Therefore the next instruction and the sequentially following instruc-
tions should have a mapping based upon the new value of CR3. (Global entries in the
TLBs are not invalidated, see Section 10.9, “Invalidating the Translation Lookaside
Buffers (TLBs)”.)
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The Pentium 4, Intel Xeon, P6 family, and Pentium processors use branch-prediction
techniques to improve performance by prefetching the destination of a branch instruction
before the branch instruction is executed. Consequently, instruction execution is not deter-
ministically serialized when a branch instruction is executed.
7.5 MULTIPLE-PROCESSOR (MP) INITIALIZATION
The IA-32 architecture (beginning with the P6 family processors) defines a multiple-processor
(MP) initialization protocol called the Multiprocessor Specification Version 1.4. This specifica-
tion defines the boot protocol to be used by IA-32 processors in multiple-processor systems.
(Here, multiple processors is defined as two or more processors.) The MP initialization
protocol has the following important features:
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It supports controlled booting of multiple processors without requiring dedicated system
hardware.
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It allows hardware to initiate the booting of a system without the need for a dedicated
signal or a predefined boot processor.
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It allows all IA-32 processors to be booted in the same manner, including those supporting
Hyper-Threading Technology.
The mechanism for carrying out the MP initialization protocol differs depending on the IA-32
processor family, as follows:
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For P6 family processors — The selection of the BSP and APs (see Section 7.5.1, “BSP
and AP Processors”) is handled through arbitration on the APIC bus, using BIPI and FIPI
messages. See Appendix C, “MP Initialization For P6 Family Processors,” for a complete
discussion of MP initialization for P6 family processors.