Intel IA-32 - Manual (Page 341)

Vol. 3A 8-17
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
The setup information that can be specified in the registers of the LVT table is as follows:
Vector Interrupt vector number.
Delivery Mode Specifies the type of interrupt to be sent to the processor. Some
delivery modes will only operate as intended when used in conjunc-
tion with a specific trigger mode. The allowable delivery modes are
as follows:
000 (Fixed) Delivers the interrupt specified in the vector field.
010 (SMI) Delivers an SMI interrupt to the processor core
through the processor’s local SMI signal path.
When using this delivery mode, the vector field
should be set to 00H for future compatibility.
100 (NMI) Delivers an NMI interrupt to the processor. The
vector information is ignored.
101 (INIT) Delivers an INIT request to the processor core,
which causes the processor to perform an INIT.
When using this delivery mode, the vector field
should be set to 00H for future compatibility.
111 (ExtINT) Causes the processor to respond to the interrupt as
if the interrupt originated in an externally connect-
ed (8259A-compatible) interrupt controller. A
special INTA bus cycle corresponding to ExtINT,
is routed to the external controller. The external
controller is expected to supply the vector infor-
mation. The APIC architecture supports only one
ExtINT source in a system, usually contained in
the compatibility bridge.
Delivery Status (Read Only)
Indicates the interrupt delivery status, as follows:
0 (Idle) There is currently no activity for this interrupt
source, or the previous interrupt from this source
was delivered to the processor core and accepted.
1 (Send Pending)
Indicates that an interrupt from this source has
been delivered to the processor core, but has not
yet been accepted (see Section 8.5.5, “Local Inter-
rupt Acceptance”).
Interrupt Input Pin Polarity
Specifies the polarity of the corresponding interrupt pin: (0) active
high or (1) active low.