Intel IA-32 - Manual (Page 287)

Vol. 3A 7-19
MULTIPLE-PROCESSOR MANAGEMENT
The following constants and data definitions are used in the accompanying code examples. They
are based on the addresses of the APIC registers as defined in Table 8-1.
ICR_LOW EQU 0FEE00300H
SVR EQU 0FEE000F0H
APIC_ID EQU 0FEE00020H
LVT3 EQU 0FEE00370H
APIC_ENABLED EQU 0100H
BOOT_ID
DD ?
COUNT EQU 00H
VACANT EQU 00H
7.5.4.1 Typical BSP Initialization Sequence
After the BSP and APs have been selected (by means of a hardware protocol, see Section 7.5.3,
“MP Initialization Protocol Algorithm for Intel Xeon Processors”), the BSP begins executing
BIOS boot-strap code (POST) at the normal IA-32 architecture starting address (FFFF FFF0H).
The boot-strap code typically performs the following operations:
1. Initializes memory.
2. Loads the microcode update into the processor.
3. Initializes the MTRRs.
4. Enables the caches.
5. Executes the CPUID instruction with a value of 0H in the EAX register, then reads the
EBX, ECX, and EDX registers to determine if the BSP is “GenuineIntel.”
6. Executes the CPUID instruction with a value of 1H in the EAX register, then saves the
values in the EAX, ECX, and EDX registers in a system configuration space in RAM for
use later.
7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1 MByte of
memory.
8. Switches to protected mode and insures that the APIC address space is mapped to the
strong uncacheable (UC) memory type.
9. Determine the BSP’s APIC ID from the local APIC ID register (default is 0):
MOV ESI, APIC_ID ; Address of local APIC ID register
MOV EAX, [ESI]
AND EAX, 0FF000000H
; Zero out all other bits except APIC ID
MOV BOOT_ID, EAX ; Save in memory
Saves the APIC ID in the ACPI and MP tables and optionally in the system configuration
space in RAM.
10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector.
The 8-bit vector defines the address of a 4-KByte page in the real-address mode address