Intel IA-32 - Manual (Page 179)

Vol. 3A 5-3
INTERRUPT AND EXCEPTION HANDLING
Table 5-1. Protected-Mode Exceptions and Interrupts
Vector
No. Mne-
monic Description Type Error
Code Source
0 #DE Divide Error Fault No DIV and IDIV instructions.
1 #DB RESERVED Fault/
Trap
No For Intel use only.
2 — NMI Interrupt Interrupt No Nonmaskable external interrupt.
3 #BP Breakpoint Trap No INT 3 instruction.
4 #OF Overflow Trap No INTO instruction.
5 #BR BOUND Range Exceeded Fault No BOUND instruction.
6 #UD Invalid Opcode (Undefined
Opcode)
Fault No UD2 instruction or reserved
opcode.
1
7 #NM Device Not Available (No
Math Coprocessor)
Fault No Floating-point or WAIT/FWAIT
instruction.
8 #DF Double Fault Abort Yes
(zero)
Any instruction that can generate
an exception, an NMI, or an
INTR.
9 Coprocessor Segment
Overrun (reserved)
Fault No Floating-point instruction. 2
10 #TS Invalid TSS Fault Yes Task switch or TSS access.
11 #NP Segment Not Present Fault Yes Loading segment registers or
accessing system segments.
12 #SS Stack-Segment Fault Fault Yes Stack operations and SS register
loads.
13 #GP General Protection Fault Yes Any memory reference and other
protection checks.
14 #PF Page Fault Fault Yes Any memory reference.
15 — (Intel reserved. Do not use.) No
16 #MF x87 FPU Floating-Point
Error (Math Fault)
Fault No x87 FPU floating-point or
WAIT/FWAIT instruction.
17 #AC Alignment Check Fault Yes
(Zero)
Any data reference in memory.
3
18 #MC Machine Check Abort No Error codes (if any) and source
are model dependent.
4
19 #XF SIMD Floating-Point
Exception
Fault No SSE/SSE2/SSE3 floating-point
instructions
5
20-31 — Intel reserved. Do not use.
32-255 — User Defined (Non-
reserved) Interrupts
Interrupt External interrupt or INT n
instruction.
NOTES:
1. The UD2 instruction was introduced in the Pentium Pro processor.
2. IA-32 processors after the Intel386 processor do not generate this exception.
3. This exception was introduced in the Intel486 processor.
4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.
5. This exception was introduced in the Pentium III processor.