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2 masking instruction breakpoints – Intel IA-32 User Manual

Page 186

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5-10 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

Manual, Volume 2A, for a detailed description of the operations these instructions are allowed
to perform on the IF flag.

5.8.2

Masking Instruction Breakpoints

The RF (resume) flag in the EFLAGS register controls the response of the processor to instruc-
tion-breakpoint conditions (see the description of the RF flag in Section 2.3, “System Flags and
Fields in the EFLAGS Register”).

When set, it prevents an instruction breakpoint from generating a debug exception (#DB); when
clear, instruction breakpoints will generate debug exceptions. The primary function of the RF
flag is to prevent the processor from going into a debug exception loop on an instruction-break-
point. See Section 18.3.1.1, “Instruction-Breakpoint Exception Condition,” for more informa-
tion on the use of this flag.

5.8.3

Masking Exceptions and Interrupts When Switching
Stacks

To switch to a different stack segment, software often uses a pair of instructions, for example:

MOV SS, AX
MOV ESP, StackTop

If an interrupt or exception occurs after the segment selector has been loaded into the SS register
but before the ESP register has been loaded, these two parts of the logical address into the stack
space are inconsistent for the duration of the interrupt or exception handler.

To prevent this situation, the processor inhibits interrupts, debug exceptions, and single-step trap
exceptions after either a MOV to SS instruction or a POP to SS instruction, until the instruction
boundary following the next instruction is reached. All other faults may still be generated. If the
LSS instruction is used to modify the contents of the SS register (which is the recommended
method of modifying this register), this problem does not occur.

5.9

PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND
INTERRUPTS

If more than one exception or interrupt is pending at an instruction boundary, the processor
services them in a predictable order. Table 5-2 shows the priority among classes of exception
and interrupt sources.