Intel IA-32 - Manual (Page 228)

5-52 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
— The RSVD flag indicates that the processor detected 1s in reserved bits of the page
directory, when the PSE or PAE flags in control register CR4 are set to 1. (The PSE
flag is only available in the Pentium 4, Intel Xeon, P6 family, and Pentium processors,
and the PAE flag is only available on the Pentium 4, Intel Xeon, and P6 family
processors. In earlier IA-32 processor, the bit position of the RSVD flag is reserved.)
— The I/D flag indicates whether the exception was caused by an instruction fetch. This
flag is reserved if the processor does not support execute-disable bit or execute disable
bit feature is not enabled (see Section 3.10).
•
The contents of the CR2 register. The processor loads the CR2 register with the 32-bit
linear address that generated the exception. The page-fault handler can use this address to
locate the corresponding page directory and page-table entries. Another page fault can
potentially occur during execution of the page-fault handler; the handler should save the
contents of the CR2 register before a second page fault can occur.
1
If a page fault is caused
by a page-level protection violation, the access flag in the page-directory entry is set when
the fault occurs. The behavior of IA-32 processors regarding the access flag in the corre-
sponding page-table entry is model specific and not architecturally defined.
Figure 5-9. Page-Fault Error Code
1. Processors update CR2 whenever a page fault is detected. If a second page fault occurs while an earlier
page fault is being delivered, the faulting linear address of the second fault will overwrite the contents of
CR2 (replacing the previous address). These updates to CR2 occur even if the page fault results in a
double fault or occurs during the delivery of a double fault.
The fault was caused by a non-present page.
The fault was caused by a page-level protection violation.
The access causing the fault was a read.
The access causing the fault was a write.
The access causing the fault originated when the processor
was executing in supervisor mode.
The access causing the fault originated when the processor
was executing in user mode.
31 0
Reserved
1 2 3 4
The fault was not caused by reserved bit violation.
The fault was caused by reserved bits set to 1 in a page directory.
P 0
1
W/R 0
1
U/S 0
RSVD 0
1
1
I/D
I/D 0 The fault was not caused by an instruction fetch.
1 The fault was caused by an instruction fetch.
P W/R U/S RSVD