Intel IA-32 - Manual (Page 256)

6-14 Vol. 3A
TASK MANAGEMENT
10. If the task switch was initiated with a CALL instruction, JMP instruction, an exception, or
an interrupt, the processor sets the busy (B) flag in the new task’s TSS descriptor; if
initiated with an IRET instruction, the busy (B) flag is left set.
11. Loads the task register with the segment selector and descriptor for the new task's TSS.
12. The TSS state is loaded into the processor. This includes the LDTR register, the PDBR
(control register CR3), the EFLAGS registers, the EIP register, the general-purpose
registers, and the segment selectors. Note that a fault during the load of this state may
corrupt architectural state.
13. The descriptors associated with the segment selectors are loaded and qualified. Any errors
associated with this loading and qualification occur in the context of the new task.
NOTES
If all checks and saves have been carried out successfully, the processor
commits to the task switch. If an unrecoverable error occurs in steps 1
through 11, the processor does not complete the task switch and insures that
the processor is returned to its state prior to the execution of the instruction
that initiated the task switch.
If an unrecoverable error occurs in step 12, architectural state may be
corrupted, but an attempt will be made to handle the error in the prior
execution environment. If an unrecoverable error occurs after the commit
point (in step 13), the processor completes the task switch (without
performing additional access and segment availability checks) and generates
the appropriate exception prior to beginning execution of the new task.
If exceptions occur after the commit point, the exception handler must finish
the task switch itself before allowing the processor to begin executing the
new task. See Chapter 5, “Interrupt 10—Invalid TSS Exception (#TS),” for
more information about the affect of exceptions on a task when they occur
after the commit point of a task switch.
14. Begins executing the new task. (To an exception handler, the first instruction of the new
task appears not to have been executed.)
The state of the currently executing task is always saved when a successful task switch occurs.
If the task is resumed, execution starts with the instruction pointed to by the saved EIP value,
and the registers are restored to the values they held when the task was suspended.