Intel IA-32 - Manual (Page 612)

17-20 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
coprocessor keeps its ERROR# output in inactive state after hardware reset; the Intel 387 copro-
cessor keeps its ERROR# output in active state after hardware reset.
Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387 math copro-
cessor signals an error condition. The P6 family, Pentium, and Intel486 processors, like the
Intel 287 coprocessor, do not.
17.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor
Initialization
When initializing an Intel486 SX processor and an Intel 487 SX math coprocessor, the initial-
ization routine should check the presence of the math coprocessor and should set the FPU related
flags (EM, MP, and NE) in control register CR0 accordingly (see Section 2.5, “Control Regis-
ters,” for a complete description of these flags). Table 17-2 gives the recommended settings for
these flags when the math coprocessor is present. The FSTCW instruction will give a value of
FFFFH for the Intel486 SX microprocessor and 037FH for the Intel 487 SX math coprocessor.
The EM and MP flags in register CR0 are interpreted as shown in Table 17-3.
Following is an example code sequence to initialize the system and check for the presence of
Intel486 SX processor/Intel 487 SX math coprocessor.
fninit
fstcw mem_loc
mov ax, mem_loc
Table 17-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX
Microprocessor/Intel 487 SX Math Coprocessor System
CR0 Flags Intel486 SX Processor Only Intel 487 SX Math Coprocessor Present
EM 1 0
MP 0 1
NE 1 0, for MS-DOS* systems
1, for user-defined exception handler
Table 17-3. EM and MP Flag Interpretation
EM MP Interpretation
0 0 Floating-point instructions are passed to FPU; WAIT/FWAIT and
other waiting-type instructions ignore TS.
0 1 Floating-point instructions are passed to FPU; WAIT/FWAIT and
other waiting-type instructions test TS.
1 0 Floating-point instructions trap to emulator; WAIT/FWAIT and
other waiting-type instructions ignore TS.
1 1 Floating-point instructions trap to emulator; WAIT/FWAIT and
other waiting-type instructions test TS.