Intel IA-32 - Manual (Page 75)

Vol. 3A 2-27
SYSTEM ARCHITECTURE OVERVIEW
Offset Is Within Limits (LSL Instruction),” for a detailed explanation of the function and use of
this instruction.
The VERR (verify for reading) and VERW (verify for writing) instructions verify if a selected
segment is readable or writable, respectively, at a given CPL. See Section 4.10.2, “Checking
Read/Write Rights (VERR and VERW Instructions),” for a detailed explanation of the function
and use of this instruction.
2.6.3 Loading and Storing Debug Registers
Internal debugging facilities in the processor are controlled by a set of 8 debug registers
(DR0-DR7). The MOV instruction allows setup data to be loaded to and stored from these
registers.
On processors that support Intel EM64T, debug registers DR0-DR7 are 64 bits. In 32-bit modes
and compatibility mode, writes to a debug register fill the upper 32 bits with zeros. Reads return
the lower 32 bits. In 64-bit mode, the upper 32 bits of DR6-DR7 are reserved and must be written
with zeros. Writing one to any of the upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register (operand-
size prefixes are ignored). All 64 bits of DR0-DR3 are writable by software. However,
MOV DRn instructions do not check that addresses written to DR0-DR3 are in the limits of the
implementation. Address matching is supported only on valid addresses generated by the
processor implementation.
2.6.4 Invalidating Caches and TLBs
The processor provides several instructions for use in explicitly invalidating its caches and TLB
entries. The INVD (invalidate cache with no writeback) instruction invalidates all data and
instruction entries in the internal caches and sends a signal to the external caches indicating that
they should be also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same function as the
INVD instruction, except that it writes back modified lines in its internal caches to memory
before it invalidates the caches. After invalidating the internal caches, WBINVD signals
external caches to write back modified data and invalidate their contents.
The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry for a spec-
ified page.
2.6.5 Controlling the Processor
The HLT (halt processor) instruction stops the processor until an enabled interrupt (such as NMI
or SMI, which are normally enabled), a debug exception, the BINIT# signal, the INIT# signal,
or the RESET# signal is received. The processor generates a special bus cycle to indicate that
the halt mode has been entered.