Intel IA-32 - Manual (Page 74)

2-26 Vol. 3A
SYSTEM ARCHITECTURE OVERVIEW
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SLDT (Store LDT Register) — Stores the LDT segment selector from the LDTR register
into memory or a general-purpose register.
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LTR (Load Task Register) — Loads segment selector and segment descriptor for a TSS
from memory into the task register. (The segment selector operand can also be located in a
general-purpose register.)
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STR (Store Task Register) — Stores the segment selector for the current task TSS from
the task register into memory or a general-purpose register.
The LMSW (load machine status word) and SMSW (store machine status word) instructions
operate on bits 0 through 15 of control register CR0. These instructions are provided for compat-
ibility with the 16-bit Intel 286 processor. Programs written to run on 32-bit IA-32 processors
should not use these instructions. Instead, they should access the control register CR0 using the
MOV instruction.
The CLTS (clear TS flag in CR0) instruction is provided for use in handling a device-not-avail-
able exception (#NM) that occurs when the processor attempts to execute a floating-point
instruction when the TS flag is set. This instruction allows the TS flag to be cleared after the x87
FPU context has been saved, preventing further #NM exceptions. See Section 2.5, “Control
Registers,” for more information on the TS flag.
The control registers (CR0, CR1, CR2, CR3, CR4, and CR8) are loaded using the MOV instruc-
tion. The instruction loads a control register from a general-purpose register or stores the content
of a control register in a general-purpose register.
2.6.2 Verifying of Access Privileges
The processor provides several instructions for examining segment selectors and segment
descriptors to determine if access to their associated segments is allowed. These instructions
duplicate some of the automatic access rights and type checking done by the processor, thus
allowing operating-system or executive software to prevent exceptions from being generated.
The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment
selector to match that of the program or procedure that supplied the segment selector. See
Section 4.10.4, “Checking Caller Access Privileges (ARPL Instruction),” for a detailed expla-
nation of the function and use of this instruction. Note that ARPL is not supported in 64-bit
mode.
The LAR (load access rights) instruction verifies the accessibility of a specified segment and
loads access rights information from the segment’s segment descriptor into a general-purpose
register. Software can then examine the access rights to determine if the segment type is compat-
ible with its intended use. See Section 4.10.1, “Checking Access Rights (LAR Instruction),” for
a detailed explanation of the function and use of this instruction.
The LSL (load segment limit) instruction verifies the accessibility of a specified segment and
loads the segment limit from the segment’s segment descriptor into a general-purpose register.
Software can then compare the segment limit with an offset into the segment to determine
whether the offset lies within the segment. See Section 4.10.3, “Checking That the Pointer