Intel IA-32 - Manual (Page 119)

Vol. 3A 3-39
PROTECTED-MODE MEMORY MANAGEMENT
3.10 PAE-ENABLED PAGING IN IA-32E MODE
Intel EM64T 64-bit extensions expand physical address extension (PAE) paging structures to
potentially support mapping a 64-bit linear address to a 52-bit physical address. In the first
implementation of Intel EM64T, PAE paging structures support translation of a 48-bit linear
address into a 40-bit physical address.
When IA-32e mode is enabled, linear address to physical address translation is different than in
PAE-enabled protected mode. Address translation from a linear address to a physical address
uses up to four levels of paging data structures. A new page mapping table, the page map level
4 table (PML4 table), is added on top of the page director pointer table.
Prior to activating IA-32e mode, PAE must be enabled by setting CR4.PAE = 1. PAE expands
the size of page-directory entries (PDE) and page-table entries (PTE) from 32 bits to 64 bits.
This change is made to support physical-address sizes of greater than 32 bits. An attempt to acti-
vate IA-32e mode prior to enabling PAE results in a general-protection exception, #GP.
PML4 tables are used in page translation only in IA-32e mode. They are not used when IA-32e
mode is disabled, whether or not PAE is enabled. The existing page-directory pointer table is
expanded to 512 eight-byte entries from four entries. As a result, nine bits of the linear address
are used to index into a PDP table rather than two bits. The size of the page-directory entry
(PDE) table and page-table entry (PTE) table remains 512 eight-byte entries, each indexed by
nine linear-address bits. The total of linear-address index bits into the collection of paging data
structures (PML4 + PDP + PDE + PTE + page offset) becomes 48. The method for translating
the high-order 16 linear-address bits into a physical address is currently reserved.
The PS flag in the page directory entry (PDE.PS) selects between 4-KByte and 2-MByte page
sizes. Because PDE.PS is used to control large page selection, the CR4.PSE bit is ignored.
3.10.1 IA-32e Mode Linear Address Translation (4-KByte Pages)
Figure 3-24 shows the PML4, page-directory-pointer, page-directory, and page-table hierarchy
when mapping linear addresses to 4-KByte pages in IA-32e mode. This paging method can be
used to address up to 2
36 pages, which spans a linear address space of 2 48 bytes.
To select the various table entries, linear addresses are divided into five sections:
•
PML4-table entry — Bits 47:39 provide an offset to an entry in the PML4 table. The
selected entry provides the base physical address of a page directory pointer table.
•
Page-directory-pointer-table entry — Bits 38:30 provide an offset to an entry in the
page-directory-pointer table. The selected entry provides the base physical address of a
page directory table.
•
Page-directory entry — Bits 29:21 provide an offset to an entry in the selected page
directory. The selected entry provides the base physical address of a page table.
•
Page-table entry — Bits 20:12 provide an offset to an entry in the selected page table.
This entry provides the base physical address of a page in physical memory.
•
Page offset — Bits 11:0 provide an offset to a physical address in the page.