Intel IA-32 - Manual (Page 303)

Vol. 3A 7-35
MULTIPLE-PROCESSOR MANAGEMENT
7.10 PROGRAMMING CONSIDERATIONS FOR HARDWARE
MULTI-THREADING CAPABLE PROCESSORS
In a multi-threading environment, there may be certain hardware resources that are physically
shared at some level of the hardware topology. In the multi-processor systems, typically bus and
memory sub-systems are physically shared between multiple sockets. Within a hardware multi-
threading capable processors, certain resources are provided for each processor core, while other
resources may be provided for each logical processors (see Section 7.8, “Intel
®
Hyper-
Threading Technology Architecture,” and Section 7.9, “Dual-Core Architecture”).
From a software programming perspective, control transfer of processor operation is managed
at the granularity of logical processor (operating systems dispatch a runnable task by allocating
an available logical processor on the platform). To manage the topology of shared resources in
a multi-threading environment, it is useful for software to understand and manage resources that
may be shared by more than one logical processors. This can be facilitated by mapping several
levels of hierarchical labels to the initial APIC_ID of each logical processor to identify the
topology of shared resources.
7.10.1 Hierarchical Mapping of Shared Resources
The initial APIC_ID value associated with each logical processor in a multi-processor system is
unique (see Section 7.7, “Detecting Hardware Multi-Threading Support and Topology”). This
8-bit value can be decomposed into sub-fields, where each sub-field corresponds a hierarchical
level of the topological mapping of hardware resources.
The decomposition of an initial APIC_ID may consist of 4 sub fields, matching 4 levels of hier-
archy:
•
Cluster — Some multi-threading environments consists of multiple clusters of multi-
processor systems. The CLUSTER_ID sub-field distinguishes different clusters. For non-
clustered systems, CLUSTER_ID is usually 0.
•
Package — A multi-processor system consists of two or more sockets, each mates with a
physical processor package. The PACKAGE_ID sub-field distinguishes different physical
packages within a cluster.
•
Core — A physical processor package consists of one or more processor cores. The
CORE_ID sub-field distinguishes processor cores in a package. For a single-core
processor, the width of this bit field is 0.
•
SMT — A processor core provides one or more logical processors sharing execution
resources. The SMT_ID sub-field distinguishes logical processors in a core. The width of
this bit field is non-zero if a processor core provides more than one logical processors.
SMT and CORE sub-fields are bit-wise contiguous in the 8-bit APIC_ID field (see Figure 7-5).
The width of each sub-field depends on hardware and software configurations. Field widths can
be determined at runtime using the algorithm discussed below (Example 7-1 through Example
7-3). Figure 7-6 depicts the relationships of three of the hierarchical sub-fields in a hypothetical
MP system.