Intel IA-32 - Manual (Page 578)

15-28 Vol. 3A
8086 EMULATION
15.4 PROTECTED-MODE VIRTUAL INTERRUPTS
The IA-32 processors (beginning with the Pentium processor) also support the VIF and VIP
flags in the EFLAGS register in protected mode by setting the PVI (protected-mode virtual
interrupt) flag in the CR4 register. Setting the PVI flag allows applications running at privilege
level 3 to execute the CLI and STI instructions without causing a general-protection exception
(#GP) or affecting hardware interrupts.
When the PVI flag is set to 1, the CPL is 3, and the IOPL is less than 3, the STI and CLI instruc-
tions set and clear the VIF flag in the EFLAGS register, leaving IF unaffected. In this mode of
operation, an application running in protected mode and at a CPL of 3 can inhibit interrupts in
the same manner as is described in Section 15.3.2, “Class 2—Maskable Hardware Interrupt
Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”, for a virtual-8086
mode task. When the application executes the CLI instruction, the processor clears the VIF flag.
If the processor receives a maskable hardware interrupt, the processor invokes the protected-
mode interrupt handler. This handler checks the state of the VIF flag in the EFLAGS register. If
the VIF flag is clear (indicating that the active task does not want to have interrupts handled
now), the handler sets the VIP flag in the EFLAGS image on the stack and returns to the privi-
lege-level 3 application, which continues program execution. When the application executes a
STI instruction to set the VIF flag, the processor automatically invokes the general-protection
exception handler, which can then handle the pending interrupt. After handing the pending inter-
rupt, the handler typically sets the VIF flag and clears the VIP flag in the EFLAGS image on the
stack and executes a return to the application program. The next time the processor receives a
maskable hardware interrupt, the processor will handle it in the normal manner for interrupts
received while the processor is operating at a CPL of 3.
As with the virtual mode extension (enabled with the VME flag in the CR4 register), the
protected-mode virtual interrupt extension only affects maskable hardware interrupts (interrupt
vectors 32 through 255). NMI interrupts and exceptions are handled in the normal manner.
When protected-mode virtual interrupts are disabled (that is, when the PVI flag in control
register CR4 is set to 0, the CPL is less than 3, or the IOPL value is 3), then the CLI and STI
instructions execute in a manner compatible with the Intel486 processor. That is, if the CPL is
greater (less privileged) than the I/O privilege level (IOPL), a general-protection exception
occurs. If the IOPL value is 3, CLI and STI clear or set the IF flag, respectively.
PUSHF, POPF, IRET and INT are executed like in the Intel486 processor, regardless of whether
protected-mode virtual interrupts are enabled.
It is only possible to enter virtual-8086 mode through a task switch or the execution of an IRET
instruction, and it is only possible to leave virtual-8086 mode by faulting to a protected-mode
interrupt handler (typically the general-protection exception handler, which in turn calls the
virtual 8086-mode monitor). In both cases, the EFLAGS register is saved and restored. This is
not true, however, in protected mode when the PVI flag is set and the processor is not in virtual-
8086 mode. Here, it is possible to call a procedure at a different privilege level, in which case
the EFLAGS register is not saved or modified. However, the states of VIF and VIP flags are
never examined by the processor when the CPL is not 3.