Intel IA-32 - Manual (Page 104)

3-24 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
To select the various table entries, the linear address is divided into three sections:
•
Page-directory entry — Bits 22 through 31 provide an offset to an entry in the page
directory. The selected entry provides the base physical address of a page table.
•
Page-table entry — Bits 12 through 21 of the linear address provide an offset to an entry
in the selected page table. This entry provides the base physical address of a page in
physical memory.
•
Page offset — Bits 0 through 11 provides an offset to a physical address in the page.
Memory management software has the option of using one page directory for all programs and
tasks, one page directory for each task, or some combination of the two.
3.7.2 Linear Address Translation (4-MByte Pages)
Figure 3-13 shows how a page directory can be used to map linear addresses to 4-MByte pages.
The entries in the page directory point to 4-MByte pages in physical memory. This paging
method can be used to map up to 1024 pages into a 4-GByte linear address space.
The 4-MByte page size is selected by setting the PSE flag in control register CR4 and setting
the page size (PS) flag in a page-directory entry (see Figure 3-14). With these flags set, the linear
address is divided into two sections:
•
Page directory entry—Bits 22 through 31 provide an offset to an entry in the page
directory. The selected entry provides the base physical address of a 4-MByte page.
•
Page offset—Bits 0 through 21 provides an offset to a physical address in the page.
Figure 3-13. Linear Address Translation (4-MByte Pages)
0
Directory Offset
Page Directory
Directory Entry
CR3 (PDBR)
4-MByte Page
Physical Address
31 21 22
Linear Address
1024 PDE = 1024 Pages
10
22
32*
*32 bits aligned onto a 4-KByte boundary.
10