Intel IA-32 - Manual (Page 480)

10-40 Vol. 3A
MEMORY CACHE CONTROL
6. If the PGE flag is set in control register CR4, flush all TLBs by clearing that flag.
7. If the PGE flag is clear in control register CR4, flush all TLBs by executing a MOV from
control register CR3 to another register and then a MOV from that register back to CR3.
8. Disable all range registers (by clearing the E flag in register MTRRdefType). If only
variable ranges are being modified, software may clear the valid bits for the affected
register pairs instead.
9. Update the MTRRs.
10. Enable all range registers (by setting the E flag in register MTRRdefType). If only
variable-range registers were modified and their individual valid bits were cleared, then set
the valid bits for the affected ranges instead.
11. Flush all caches and all TLBs a second time. (The TLB flush is required for Pentium 4,
Intel Xeon, and P6 family processors. Executing the WBINVD instruction is not needed
when using Pentium 4, Intel Xeon, and P6 family processors, but it may be needed in
future systems.)
12. Enter the normal cache mode to re-enable caching. (Set the CD and NW flags in control
register CR0 to 0.)
13. Set PGE flag in control register CR4, if cleared in Step 6 (above).
14. Wait for all processors to reach this point.
15. Enable interrupts.
10.11.9 Large Page Size Considerations
The MTRRs provide memory typing for a limited number of regions that have a 4 KByte gran-
ularity (the same granularity as 4-KByte pages). The memory type for a given page is cached in
the processor’s TLBs. When using large pages (2 or 4 MBytes), a single page-table entry covers
multiple 4-KByte granules, each with a single memory type. Because the memory type for a
large page is cached in the TLB, the processor can behave in an undefined manner if a large page
is mapped to a region of memory that MTRRs have mapped with multiple memory types.
Undefined behavior can be avoided by insuring that all MTRR memory-type ranges within a
large page are of the same type. If a large page maps to a region of memory containing different
MTRR-defined memory types, the PCD and PWT flags in the page-table entry should be set for
the most conservative memory type for that range. For example, a large page used for memory
mapped I/O and regular memory is mapped as UC memory. Alternatively, the operating system
can map the region using multiple 4-KByte pages each with its own memory type.
The requirement that all 4-KByte ranges in a large page are of the same memory type implies
that large pages with different memory types may suffer a performance penalty, since they must
be marked with the lowest common denominator memory type.