Intel IA-32 - Manual (Page 541)

Vol. 3A 14-15
MACHINE-CHECK ARCHITECTURE
For example, the error code ICACHEL1_RD_ERR is constructed from the form:
{TT}CACHE{LL}_{RRRR}_ERR,
where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD.
The 2-bit TT sub-field (Table 14-5) indicates the type of transaction (data, instruction, or
generic). The sub-field applies to the TLB, cache, and interconnect error conditions. Note that
interconnect error conditions are primarily associated with P6 family and Pentium processors,
which utilize an external APIC bus separate from the system bus. The generic type is reported
when the processor cannot determine the transaction type.
The 2-bit LL sub-field (see Table 14-6) indicates the level in the memory hierarchy where the
error occurred (level 0, level 1, level 2, or generic). The LL sub-field also applies to the TLB,
cache, and interconnect error conditions. The Pentium 4, Intel Xeon, and P6 family processors
support two levels in the cache hierarchy and one level in the TLBs. Again, the generic type is
reported when the processor cannot determine the hierarchy level.
Table 14-4. IA32_MCi_Status [15:0] Compound Error Code Encoding
Type Form Interpretation
TLB Errors 0000 0000 0001 TTLL {TT}TLB{LL}_ERR
Memory Hierarchy Errors 0000 0001 RRRR TTLL {TT}CACHE{LL}_{RRRR}_ERR
Bus and Interconnect
Errors 0000 1PPT RRRR IILL BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR
Internal Timer 0000 0100 0000 0000
Table 14-5. Encoding for TT (Transaction Type) Sub-Field
Transaction Type Mnemonic Binary Encoding
Instruction I 00
Data D 01
Generic G 10
Table 14-6. Level Encoding for LL (Memory Hierarchy Level) Sub-Field
Hierarchy Level Mnemonic Binary Encoding
Level 0 L0 00
Level 1 L1 01
Level 2 L2 10
Generic LG 11