Intel IA-32 - Manual (Page 499)

Vol. 3A 12-1
CHAPTER 12
SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING
This chapter describes features of the streaming SIMD extensions (SSE), streaming SIMD
extensions 2 (SSE2) and streaming SIMD extensions 3 (SSE3) that must be considered when
designing or enhancing an operating system to support the Pentium III, Pentium 4, and Intel
Xeon processors. It covers enabling SSE/SSE2/SSE3 extensions, providing operating system or
executive support for the SSE/SSE2/SSE3 extensions, SIMD floating-point exceptions, excep-
tion handling, and task (context) switching considerations.
12.1 PROVIDING OPERATING SYSTEM SUPPORT FOR
SSE/SSE2/SSE3 EXTENSIONS
To use SSE/SSE2/SSE3 extensions, the operating system or executive must provide support for
initializing the processor to use the extensions, for handling the FXSAVE and FXRSTOR state
saving instructions, and for handling SIMD floating-point exceptions. The following sections
give some guidelines for providing this support in an operating-system or executive. Because
SSE/SSE2/SSE3 extensions share the same state and perform companion operations, these
guidelines apply to all three sets of extensions.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE3),” and Chapter 12,
“Programming with Streaming SIMD Extensions 3 (SSE3),” in the IA-32 Intel® Architecture
Software Developer’s Manual, Volume 1, discuss support for SSE/SSE2/SSE3 extensions from
the point of view of an applications program.
12.1.1 Adding Support to an Operating System for
SSE/SSE2/SSE3 Extensions
The following guidelines describe operations that an operating system or executive must
perform to support SSE/SSE2/SSE3 extensions:
1. Check that the processor supports the SSE/SSE2/SSE3 extensions.
2. Check that the processor supports the FXSAVE and FXRESTOR instructions.
3. Provide an initialization for the SSE, SSE2 and SSE3 states.
4. Provide support for the FXSAVE and FXRSTOR instructions.
5. Provide support (if necessary) in non-numeric exception handlers for exceptions generated
by the SSE and SSE2 instructions.
6. Provide an exception handler for the SIMD floating-point exception (#XF).
The following sections describe how to implement each of these guidelines.