Intel IA-32 - Manual (Page 292)

7-24 Vol. 3A
MULTIPLE-PROCESSOR MANAGEMENT
7.7 DETECTING HARDWARE MULTI-THREADING SUPPORT
AND TOPOLOGY
Use the CPUID instruction to detect the presence of hardware multi-threading support in a phys-
ical processor. The following can be interpreted:
•
Hardware Multi-Threading feature flag (CPUID.1:EDX[28] = 1) — Indicates when set
that the physical package is capable of supporting Hyper-Threading Technology and/or
multiple cores.
•
Logical processors per Package (CPUID.1:EBX[23:16]) — Indicates the maximum
number of logical processors in a physical package. This represents the hardware
capability as the processor has been manufactured.
2
•
Cores per Package
3
(CPUID.4:EAX[31:26] + 1) — The maximum number of cores in a
physical package is indicated by one plus the decimal value represented in
CPUID.4:EAX[31:26].
The CPUID feature flag may indicate support for hardware multi-threading when only one
logical processor available in the package. In this case, the decimal value represented by bits 16
through 23 in the EBX register will have a value of 1.
Software should note that the number of logical processors enabled by system software may be
less than the value of “logical processors per package”. Similarly, the number of cores enabled
by system software may be less than the value of “cores per package”.
7.7.1 Initializing IA-32 Processors
Supporting Hyper-Threading Technology
The initialization process for an MP system that contains IA-32 processors that support Hyper-
Threading Technology is the same as for conventional MP systems (see Section 7.5, “Multiple-
Processor (MP) Initialization”). One logical processor in the system is selected as the BSP and
other processors (or logical processors) are designated as APs. The initialization process is iden-
tical to that described in Section 7.5.3, “MP Initialization Protocol Algorithm for
Intel Xeon Processors,” and Section 7.5.4, “MP Initialization Example.”
During initialization, each logical processor is assigned an APIC ID that is stored in the local
APIC ID register for each logical processor. If two or more processors supporting Hyper-
Threading Technology are present, each logical processor on the system bus is assigned a unique
ID (see Section 7.10.2, “Identifying Logical Processors in an MP System”). Once logical
processors have APIC IDs, software communicates with them by sending APIC IPI messages.
2. Operating system and BIOS may implement features that reduce the number of logical processors avail-
able in a platform to applications at runtime to less than the number of physical packages times the num-
ber of hardware-capable logical processors per package.
3. Software must check CPUID for its support of leaf 4 when implementing support for multi-core. If CPUID
leaf 4 is not available at runtime, software should handle the situation as if there is only one core per pack-
age.