Intel IA-32 - Manual (Page 70)

2-22 Vol. 3A
SYSTEM ARCHITECTURE OVERVIEW
VME Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and exception-
handling extensions in virtual-8086 mode when set; disables the extensions when clear.
Use of the virtual mode extensions can improve the performance of virtual-8086 appli-
cations by eliminating the overhead of calling the virtual-8086 monitor to handle inter-
rupts and exceptions that occur while executing an 8086 program and, instead,
redirecting the interrupts and exceptions back to the 8086 program’s handlers. It also
provides hardware support for a virtual interrupt flag (VIF) to improve reliability of
running 8086 programs in multitasking and multiple-processor environments.
See also: Section 15.3, “Interrupt and Exception Handling in Virtual-8086 Mode.”
PVI Protected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardware support for
a virtual interrupt flag (VIF) in protected mode when set; disables the VIF flag in
protected mode when clear.
See also: Section 15.4, “Protected-Mode Virtual Interrupts.”
TSD Time Stamp Disable (bit 2 of CR4) — Restricts the execution of the RDTSC instruc-
tion to procedures running at privilege level 0 when set; allows RDTSC instruction to
be executed at any privilege level when clear.
DE Debugging Extensions (bit 3 of CR4) — References to debug registers DR4 and DR5
cause an undefined opcode (#UD) exception to be generated when set; when clear,
processor aliases references to registers DR4 and DR5 for compatibility with software
written to run on earlier IA-32 processors.
See also: Section 18.2.2, “Debug Registers DR4 and DR5.”
PSE Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages when set; restricts
pages to 4 KBytes when clear.
See also: Section 3.6.1, “Paging Options.”
PAE Physical Address Extension (bit 5 of CR4) — When set, enables paging mechanism
to reference greater-or-equal-than-36-bit physical addresses. When clear, restricts
physical addresses to 32 bits. PAE must be enabled to enable IA-32e mode operation.
Enabling and disabling IA-32e mode operation also requires modifying CR4.PAE.
See also: Section 3.8, “36-Bit Physical Addressing Using the PAE Paging
Mechanism.”
MCE Machine-Check Enable (bit 6 of CR4) — Enables the machine-check exception
when set; disables the machine-check exception when clear.
See also: Chapter 14, “Machine-Check Architecture.”
PGE Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family processors.)
Enables the global page feature when set; disables the global page feature when clear.
The global page feature allows frequently used or shared pages to be marked as global
to all users (done with the global flag, bit 8, in a page-directory or page-table entry).
Global pages are not flushed from the translation-lookaside buffer (TLB) on a task
switch or a write to register CR3.