Avago Technologies LSI53C1030 User Manual

Page 99

PCI Configuration Space Register Description

4-13

Version 2.2

tinguish their cards from one another even if the cards
use the same PCI controller (and have the same Vendor
ID and Device ID). The board designer can store a ven-
dor specific, 16-bit value in an external serial EEPROM.

The ID Control Power-On Sense pins (MAD[11] for PCI
Function [1]; MAD[10] for PCI Function [0]) and the serial
EEPROM enable Power-On Sense pin (MAD[7]) control
the value of this register. These pins have internal pull
downs. Allowing MAD[7] to remain internally pulled down
enables the serial EEPROM interface and permits the
LSI53C1030 to load this register from the serial EEPROM
at power up. Pulling MAD[7] HIGH disables the serial
EEPROM interface. Allowing the ID Control pins to
remain internally pulled LOW has no effect on this regis-
ter. Pulling the ID Control pins HIGH sets bit [15] of this
register for the given PCI function. Pulling the ID Control
pins HIGH takes precedence over all other settings for
bit [15].

Table 4.2

lists the configuration options for the Power-On

Sense pins and settings for this register. If the serial
EEPROM interface is disabled and the ID Control pins
are internally pulled LOW, this register contains 0x1000.
If the serial EEPROM interface is disabled and the ID
Control pins are pulled HIGH, this register contains
0x8000. If a download from the serial EEPROM fails and
the ID Control pins are internally pulled LOW, this register
contains 0x0000. If a download from the serial EEPROM
fails and the ID Control pins are pulled HIGH, this register
contains 0x8000. Refer to

Section 3.10, “Power-On

Sense Pins Description,”

for additional information.

Table 4.2

Subsystem ID Register Download Conditions and Values

MAD[7] State

MAD[11] or MAD[10] LOW

MAD[11] or MAD[10] HIGH

MAD[7] LOW

Subsystem ID

= 0xXXXX

Bits [15:0] are downloaded.