Avago Technologies LSI53C1030 - Manual (Page 156)

IX-2 Index
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
BIOS 2-8 , 2-27
bit
133 MHz capable 4-27
64-bit address capable 4-21
64-bit device 4-27
66 MHz capable 4-6
aux current 4-18
bus number 4-28
D1 support 4-18
D2 support 4-18
data parity error recovery enable 4-26
data parity error reported 4-6
data scale 4-19
data select 4-19
designed maximum cumulative read size 4-26
designed maximum memory read byte count 4-27
designed maximum outstanding split transactions
4-26
detected parity error (from slave) 4-5
device complexity 4-27
device number 4-28
device specific initialization 4-18
DEVSEL/ timing 4-5
diagnostic memory enable 4-32
diagnostic read/write enable 4-32
diagnostic write enable 4-31 , 4-34
DisARM 4-32
doorbell interrupt mask 4-37
enable bus mastering 4-4
enable I/O 4-5
enable memory space 4-4
enable parity error response 4-4
expansion ROM enable 4-14
flash ROM bad signature 4-32
function number 4-28
interrupt request routing mode 4-36
IOP doorbell status 4-35
MSI enable 4-22
multiple message 4-22
new capabilities 4-6
PME clock 4-18
PME enable 4-19
PME status 4-19
PME support 4-18
power management version 4-18
power state 4-19
received master abort (from master) 4-5
received split completion error message 4-26
received target abort (from master) 4-5
reply interrupt 4-35
reply interrupt mask 4-36
reset adapter 4-32
reset history 4-31 , 4-32
SERR/ enable 4-4
signalled system error 4-5
system doorbell interrupt 4-35
TTL interrupt 4-32
unexpected split completion 4-27
write and invalidate enable 4-4
block diagram 2-3
board application 1-3
boot device 2-5 , 2-24
boundary scan 1-13
burst size selection 2-13
bus
mastering 2-15 , 2-17
number 4-28
PCI commands 2-10
training 1-10
BWE[1:0]/ 3-15 , 5-6
C
C_BE[3:0]/ 2-8 , 2-9 , 2-10 , 2-12 , 5-5
C_BE[7:0]/ 3-5 , 5-5
cache line size 1-11 , 2-13 , 2-14 , 4-7
alignment 2-14
register 2-15 , 4-7
capabilities pointer register 4-14
capability ID 4-2
MSI 4-20
PCI-X 4-24
power management 4-17
capacitance
input 5-4
checksum 2-27 , 2-28
class code register 4-7
CLK 3-4 , 5-6
CLKMODE_0 3-18 , 3-25 , 5-6
CLKMODE_1 3-18 , 3-25 , 5-6
clock
EEPROM 3-16 , 3-25
external 5-9
PCI 5-9
PME 4-18
SCLK 3-10 , 5-9
SCSI 3-10
skew control 2-22
CLS 4-7
CLS alignment 2-14
command register 2-18 , 4-3
common mode voltage 5-3
completer ID 4-28
configuration
parameters 2-24
read command 2-8 , 2-10 , 2-12 , 2-13 , 4-6