Avago Technologies LSI53C1030 - Manual (Page 134)

5-10 Specifications
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.5 External Clock
Table 5.14 and Figure 5.6 provide reset input timing data.
Figure 5.6 Reset Input
Table 5.15 and Figure 5.7 provide Interrupt Output timing data.
CLK, SCLK 1.4 V
t
1
t
3
t
4
t
2
Table 5.14 Reset Input
Symbol Parameter Min Max Units
t
1
Reset pulse width 10 – ns
t
2
Reset deasserted setup to CLK HIGH 0 – ns
t
3
MAD setup time to CLK HIGH (for configuring the MAD bus only) 20 – ns
t
4
MAD hold time from CLK HIGH (for configuring the MAD bus only) 20 – ns
Table 5.15 Interrupt Output
Symbol Parameter Min Max Units
t
1
CLK HIGH to IRQ/ LOW 2 11 ns
t
2
CLK HIGH to IRQ/ HIGH 2 11 ns
t
3
IRQ/ deassertion time 3 – CLK
t
1
t
2
t
3
t
4
CLK
RST/
MAD*
*When enabled
Valid
Data