Avago Technologies LSI53C1030 - Manual (Page 94)

4-8 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
for performing write cycles. Programming this register to
a number other than a nonzero power of two disables the
the use of the PCI performance commands to execute
data transfers. The PCI function ignores this register
when operating in the PCI-X mode.
Reserved [2:0]
This field is reserved.
Register: 0x0D
Latency Timer
Read/Write
Latency Timer [7:4]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. If the LSI53C1030 initializes in the PCI mode, the
default value of this register is 0x00. If the LSI53C1030
initializes in the PCI-X mode, the default value of this reg-
ister is 0x40.
Reserved [3:0]
This field is reserved.
Register: 0x0E
Header Type
Read Only
Header Type [7:0]
This 8-bit register identifies the layout of bytes 0x10
through 0x3F in configuration space and also indicates if
the device is a single function or multifunction PCI device.
If the LSI53C1030 is configured as a multifunction PCI
device, bit 7 is set. If the LSI53C1030 is configured as a
single function PCI device, bit 7 is cleared.
7 4 3 0
Latency Timer
0 X 0 0 0 0 0 0
7 0
Header Type
X 0 0 0 0 0 0 0