Status – Avago Technologies LSI53C1030 User Manual
Page 91
PCI Configuration Space Register Description
4-5
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Enable I/O Space
0
This bit controls the LSI53C1030 PCI function’s response
to I/O Space accesses. Setting this bit enables the PCI
function to respond to I/O Space accesses at the address
range the PCI Configuration Space
register specifies. Clearing this bit disables the PCI func-
tion’s response to I/O Space accesses.
Register: 0x06–0x07
Status
Read/Write
Reads to this register behave normally. To clear a bit location that is
currently set, write the bit to one (1). For example, to clear bit 15 when
it is set, without affecting any other bits, write 0x8000 to the register.
Detected Parity Error (from Slave)
15
This bit is set per the PCI Local Bus Specification, Revi-
sion 2.2, and PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0a.
Signalled System Error
14
The LSI53C1030 PCI function sets this bit when assert-
ing the SERR/ signal.
Received Master Abort (from Master)
13
A master device sets this bit when a Master Abort com-
mand terminates its transaction (except for Special
Cycle).
Received Target Abort (from Master)
12
A master device sets this bit when a Target Abort com-
mand terminates its transaction.
Reserved
11
This bit is reserved.
DEVSEL/ Timing
[10:9]
These two read only bits encode the timing of DEVSEL/
and indicate the slowest time that a device asserts
15
14
13
12
11
10
9
8
7
6
5
4
3
0
Status
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0