Avago Technologies LSI53C1030 - Manual (Page 93)

PCI Configuration Space Register Description 4-7
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0x08
Revision ID
Read/Write
Revision ID [7:0]
This register indicates the current revision level of the
device.
Register: 0x09–0x0B
Class Code
Read Only
Class Code [23:0]
This 24-bit register identifies the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register-level programming inter-
face. The value of this register is 0x010000, which iden-
tifies a SCSI controller.
Register: 0x0C
Cache Line Size
Read/Write
Cache Line Size [7:3]
This register specifies the system cache line size in units
of 32-bit words. In the conventional PCI mode, the
LSI53C1030 PCI function uses this register to determine
whether to use Write and Invalidate or Write commands
7 0
Revision ID
X X X X X X X X
23 0
Class Code
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 3 2 0
Cache Line Size
0 0 0 0 0 0 0 0