Avago Technologies LSI53C1030 - Manual (Page 108)

4-22 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Multiple Message Capable [3:1]
These read only bits indicate the number of messages
that the LSI53C1030 requests from the host. The host
system software reads this field to determine the number
of requested messages. The number of requested mes-
sages must align to a power of two. The LSI53C1030
sets this field to 0b000 to request one message. All other
encodings of this field are reserved.
MSI Enable 0
System software sets this bit to enable MSI. Setting this
bit enables the device to use MSI to interrupt the host
and request service. Setting this bit also prohibits the
device from using the INTx/ or ALT_INTx/ pins to request
service from the host. Setting this bit to mask interrupts
on the INTx/ or ALT_INTx/ pins is a violation of the PCI
specification.
Register: 0xXX
Message Address
Read/Write
Table 4.3 Multiple Message Enable Field Bit Encoding
Bits [6:4] Encoding Number of Allocated Messages
0b000 1
0b001 2
0b010 4
0b011 8
0b100 16
0b101 32
0b110 Reserved
0b111 Reserved
31 2 1 0
Message Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0