Avago Technologies LSI53C1030 - Manual (Page 115)

PCI I/O Space and Memory Space Register Description 4-29
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Table 4.7 defines the PCI Memory Space [0] address map.
Table 4.8 defines the PCI Memory Space [1] address map.
A bit level description of the PCI Memory and PCI I/O Spaces follows.
Table 4.6 PCI I/O Space Address Map
31 0 Offset Page
System Doorbell 0x0000 4-30
Write Sequence 0x0004 4-30
Host Diagnostic 0x0008 4-31
Test Base Address 0x000C 4-33
Diagnostic Read/Write Data 0x0010 4-33
Diagnostic Read/Write Address 0x0014 4-34
Reserved 0x0018–0x002F –
Host Interrupt Status 0x0030 4-35
Host Interrupt Mask 0x0034 4-36
Reserved 0x0038–0x003F –
Request FIFO 0x0040 4-37
Reply FIFO 0x0044 4-37
Reserved 0x0048–0x007F –
Table 4.7 PCI Memory [0] Address Map
31 0 Offset Page
System Doorbell 0x0000 4-30
Write Sequence 0x0004 4-30
Host Diagnostic 0x0008 4-31
Test Base Address 0x000C 4-33
Reserved 0x0010–0x002F –
Host Interrupt Status 0x0030 4-35
Host Interrupt Mask 0x0034 4-36
Reserved 0x0038–0x003F –
Request FIFO 0x0040 4-37
Reply FIFO 0x0044 4-37
Reserved 0x0048–0x007F –
Shared Memory
0x0080–
0x(Sizeof(Mem0)
−
1)
–
Table 4.8 PCI Memory [1] Address Map
31 0
Diagnostic Memory
0x0000–
0x(Sizeof(Mem1)
−
1)