Avago Technologies LSI53C1030 - Manual (Page 52)

2-22 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
overhead and maximizes bus bandwidth by skipping the bus free phase
that normally follows a SCSI connection.
To perform QAS, the target sends a QAS request message to the initiator
during the message phase of the bus. QAS capable devices snoop the
SCSI bus for the QAS request message. If a QAS request message is
seen, devices can immediately move to the arbitration phase without
going to the bus free phase. The LSI53C1030 employs a fairness
algorithm to ensure that all devices have equal bus access.
2.4.1.6 Skew Compensation
The LSI53C1030 provides a method to account for and control system
skew between the clock and data signals. Skew compensation is only
available when the device operates in the Ultra320 SCSI mode. The
initiator-target pair uses the training sequences in the SPI-4 draft
standard to determine the skew compensation. Depending on the state
of the RTI bit in the PPR negotiation, the LSI53C1030 can either execute
this training pattern during each connection, or can execute the training
pattern, store the adjustment parameters, and recall them on subsequent
connections with the given device. The target determines when to
execute the training pattern.
2.4.1.7 Cyclic Redundancy Check (CRC)
Ultra320 SCSI and Ultra160 SCSI devices employ CRC as an error
detection code during the DT Data phases. These devices transfer four
CRC bytes during the DT Data phases to ensure reliable data transfers.
2.4.1.8 SureLINK Domain Validation
SureLINK Domain Validation establishes the integrity of a SCSI bus
connection between an initiator and a target. Under the SureLINK
Domain Validation procedure, a host queries a device to determine its
ability to communicate at the negotiated data transfer rate.
SureLINK Domain Validation provides 3 levels of integrity checking: Basic
(Level 1) with inquiry command, Enhanced (Level 2) with read/write
buffer, and Margined (Level 3) with drive strength margining and slew
rate control. The basic check consists of an inquiry command to detect
gross problems. The enhanced check sends a known data pattern using
the read and write buffer commands to detect additional problems. The