Avago Technologies LSI53C1030 - Manual (Page 45)

PCI Functional Description 2-15
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.3.2.18 Memory Write Block Command
The LSI53C1030 uses this command to burst data to memory. The
LSI53C1030 supports this command when operating in the PCI-X bus
mode.
2.3.3 PCI Arbitration
The LSI53C1030 contains independent bus mastering functions for each
of the SCSI functions and for the system interface. The system interface
bus mastering function manages DMA operations as well as the request
and reply message frames. The SCSI channel bus mastering functions
manage data transfers across the SCSI channels.
The LSI53C1030 uses a single REQ/-GNT/ signal pair to arbitrate for
access to the PCI bus. To ensure fair access to the PCI bus, the internal
arbiter uses a round robin arbitration scheme to decide which of the three
internal bus mastering functions can arbitrate for access to the PCI bus.
2.3.4 PCI Cache Mode
The LSI53C1030 supports an 8-bit Cache Line Size register. The Cache
Line Size register provides the ability to sense and react to nonaligned
addresses corresponding to cache line boundaries. The LSI53C1030
determines when to issue a PCI cache command (Memory Read Line,
Memory Read Multiple, and Memory Write and Invalidate), or PCI
noncache command (Memory Read or Memory Write command).
2.3.5 PCI Interrupts
The LSI53C1030 signals an interrupt to the host processor either using
PCI interrupt pins, INTx/ and ALT_INTx/, or using Message Signalled
Interrupts (MSI). If using the PCI interrupt pins, the Interrupt Request
Routing Mode bits in the
Host Interrupt Mask register configure the
routing of each interrupt to either the INTx/ and/or the ALT_INTx/ pin.
The
Interrupt Pin register configures the routing of each PCI function’s
interrupt signals to either the interrupt A pins (INTA/, ALT_INTA/) or the
interrupt B pins (INTB/ or ALT_INTB/).
If using MSI, the LSI53C1030 does not signal interrupts on INTx/ or
ALT_INTx/. Note that enabling MSI to mask PCI interrupts is a violation
of the PCI specification. Each PCI function of the LSI53C1030