Avago Technologies LSI53C1030 - Manual (Page 165)

Index IX-11
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
flash ROM/NVSRAM interface 3-14
GPIO 3-19
ground 3-20
input 5-6
LED 3-19
memory interface 3-14
PCI address and data 3-5
PCI arbitration 3-7
PCI error reporting 3-7
PCI interface control 3-6
PCI interrupt 3-8
PCI system 3-4
PCI-related 3-9
power 3-20
power-on sense 3-21
pull-ups and pull-downs 3-25
SCSI channel [0] control 3-12
SCSI channel [0] interface 3-10
SCSI channel [1] control 3-14
SCSI channel [1] interface 3-13
SCSI interface 3-10
serial EEPROM interface 3-16
test interface 3-17
zero channel RAID interface 3-16
signature recognition 2-25
single ended SCSI 2-23
single ended SCSI signals 5-7
SIO+- 5-3
SISL 1-11
skew compensation 1-2 , 1-7 , 1-10 , 2-22
slew rate 1-8 , 1-10 , 1-13 , 2-22 , 5-8 , 5-9
SMSG+- 5-3
special cycle command 2-10 , 2-11 , 4-5
split completion command 1-11 , 2-10 , 2-13
split completion discarded bit 4-27
split completion error 4-26
split completion received error message 4-26
split completion unexpected 4-27
split transaction 1-11 , 4-26
SREQ+- 5-3
SRST+- 5-3
SSEL+- 5-3
status
IOP doorbell bit 4-35
register 4-5 , 4-26
STOP/ 3-6 , 5-5
stress ratings 5-2
subsystem ID 2-27 , 2-28 , 3-22 , 3-23 , 4-13
subsystem ID register 4-12
subsystem vendor ID 2-27 , 2-28 , 3-23
subsystem vendor ID register 4-12
supply current 5-2
supply voltage 5-2
SureLINK 1-2 , 1-8 , 1-13 , 2-22 , 2-23
system address space 4-1
system application 1-4
system BIOS 2-8 , 2-27
system doorbell 2-16 , 4-35
system doorbell interrupt bit 4-35
system doorbell register 4-30
system interface 2-4 , 2-15
bus mastering function 2-15
doorbell 2-6
T
Ta 5-2
target abort 4-5
TCK_CHIP 3-17 , 3-25 , 5-6
TCK_ICE 2-30 , 3-17 , 3-25 , 5-6
TDI_CHIP 3-17 , 3-25 , 5-6
TDI_ICE 2-30 , 3-17 , 3-25 , 5-6
TDO_CHIP 3-17 , 5-6
TDO_ICE 2-30 , 3-17 , 5-6
temperature
junction 5-2
lead 5-2
operating free air 5-2
storage 5-2
termination 2-23
test base address register 4-33
test condition 5-8
test interface 2-30 , 3-17
testability 1-13
TESTACLK 3-18 , 3-25 , 5-6
TESTCLKEN 3-18 , 3-25 , 5-6
TESTHCLK 3-18 , 3-25 , 5-6
TestReset/ 4-32
thermal resistance 5-2
timer 2-5
timing
external memory 5-11
interrupt output 5-10
PCI and PCI-X 5-9
power-up 5-11
reset 5-10
timing diagrams 5-11
Tj 5-2
TMS_CHIP 3-17 , 3-25 , 5-6
TMS_ICE 2-30 , 3-17 , 3-25 , 5-6
TN 3-18 , 3-25 , 5-6
TolerANT 1-9 , 1-13 , 5-7
TRACECLK 3-17 , 5-6
TRACEPKT[7:0] 3-17 , 5-6
TRACESYNC 3-17 , 5-6
transfer period 2-18