Avago Technologies LSI53C1030 - Manual (Page 159)

Index IX-5
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
INTB/ 2-15
line register 4-15
message signalled 2-15 , 2-16
message singalled 2-16
MSI 1-12
output 5-10
PCI 2-15
pin register 4-16
pins 2-15
reply 2-16
reply bit 4-35
reply mask bit 4-36
request routing mode bits 4-36
service routine 1-11
signal routing 4-36
system doorbell 2-16 , 4-35
system doorbell bit 4-35
TTL bit 4-32
intersymbol interference 1-7 , 1-13
IOP 2-4 , 2-5 , 2-6 , 2-7 , 3-21 , 4-30 , 4-32 , 4-35
boot 3-21 , 3-23
IOP doorbell status bit 4-35
IOPD_GNT/ 2-28 , 3-16 , 3-25 , 5-6
IRDY/ 3-6 , 5-5
IS 1-4
ISI 1-7 , 1-13 , 2-19
ISR 1-11
IU_Request 2-18
J
JTAG 1-13 , 3-17
junction temperature 5-2
K
key
I/O 4-31 , 4-34
L
latch-up current 5-2 , 5-8
latch-up protection 1-13
latency timer 4-8
latency timer register 4-8
lead temperature 5-2
LED 2-5 , 3-19
low voltage differential 2-23
LSI53C1010R 1-12 , 2-29
LVD 1-12 , 2-23 , 3-10 , 3-11 , 3-13
driver 5-3
driver SCSI signals 5-3
receiver SCSI signals 5-3
receiver voltage 5-3
sense voltage 5-4
LVDlink 1-3 , 1-8 , 1-12 , 2-18 , 2-23
M
MAD[10] 4-13
MAD[11] 4-13
MAD[13] 4-6
MAD[14] 4-27
MAD[15:0] 2-5 , 3-15 , 3-21 , 3-25 , 5-5
MAD[15] 4-27
MAD[2:1] 2-24
MAD[3] 2-26
MAD[7:0] 2-5 , 2-24 , 3-15
MAD[7] 4-12 , 4-13
MADP[0] 2-5
MADP[1:0] 2-5 , 3-15 , 3-21 , 3-25 , 5-5
margin control settings 2-18
master abort 4-5
master data parity error 4-26
max_lat 4-17
maximum latency register 4-17
maximum memory read byte count bits 4-25
maximum outstanding split transactions bits 4-24
maximum stress ratings 5-2
MCLK 3-14 , 5-6
MCS 2-18
mechanical drawing 5-26
memory
alias to read block 2-12 , 2-13
alias to write block 2-10 , 2-12
controller 2-5
flash ROM size 3-24
read block command 1-11 , 2-10 , 2-12 , 2-13 , 2-14
read command 2-10 , 2-11 , 2-13 , 2-14 , 2-15
read dword command 1-11 , 2-10 , 2-11 , 2-13
read line command 1-11 , 2-10 , 2-14 , 2-15
read multiple command 1-11 , 2-10 , 2-13 , 2-15
signal interface 3-14
space 2-9 , 4-1 , 4-28
space description 4-28
write and invalidate command 1-11 , 2-10 , 2-14 ,
2-15
write block command 1-11 , 2-10 , 2-12 , 2-15
write command 2-10 , 2-11 , 2-14 , 2-15
memory [0] high 4-4 , 4-10
memory [0] low 4-4 , 4-9
memory [1] high 4-4 , 4-11
memory [1] low 4-4 , 4-10
memory read 4-27
memory space 2-9 , 4-28
message address register 4-22
message control register 4-21