Avago Technologies LSI53C1030 - Manual (Page 162)

IX-8 Index
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
data scale bit 4-19
data select bit 4-19
device specific initialization bit 4-18
event 4-18
interface 1-11
next pointer register 4-17
PME clock bit 4-18
PME enable bit 4-19
PME status bit 4-19
power state bit 4-19
support bits 4-18
version bit 4-18
power signals 3-20
power state
D0 2-16 , 2-17
D1 2-16 , 2-17
D2 2-16 , 2-17
D3 2-16 , 2-17 , 2-18 , 4-19
power state bit 4-19
power-on reset 4-32
power-on sense pins 3-21
PPR 2-18 , 2-20 , 2-22
precompensation 1-2 , 2-18 , 2-20
pull-ups and pull-downs 3-25
PVT1, PVT2 3-9 , 5-6
Q
QAS 1-2 , 1-10 , 2-18 , 2-21
queue
message 2-7
reply message 2-5 , 2-7
request message 2-5 , 2-7
quick arbitration and selection 1-2 , 1-10 , 2-18 , 2-21
R
RAID 2-28 , 3-16
RAMCE/ 2-26 , 3-15 , 5-6
read streaming 2-18
received master abort (from master) bit 4-5
received split completion error message bit 4-26
received target abort (from master) bit 4-5
register
cache line size 4-7
capabilities pointer 4-14
class code 4-7
command 2-18 , 4-3
device ID 4-3
diagnostic read/write address 4-34
diagnostic read/write data 4-33
expansion ROM base address 4-14
header type 4-8
host diagnostic 4-31
host interrupt mask 2-16 , 3-8 , 3-9 , 4-36
host interrupt status 4-35
I/O base address 4-9
interrupt line 4-15
interrupt pin 4-16
latency timer 4-8
maximum latency 4-17
memory [0] high 4-10
memory [0] low 4-9
memory [1] high 4-11
memory [1] low 4-10
message address 4-22
message control 4-21
message data 4-23
message upper address 4-23
minimum grant 4-16
MSI capability ID 4-20
MSI next pointer 4-21
PCI memory [0] address map 4-29
PCI memory [1] address map 4-29
PCI-X capability ID 4-24
PCI-X command 4-24
PCI-X next pointer 4-24
PCI-X status 4-26
power management bridge support extensions 4-20
power management capabilities 4-18
power management capability ID 4-17
power management control/status 2-16 , 4-19
power management data 4-20
power management next pointer 4-17
reply FIFO 4-37
request FIFO 4-37
revision ID 4-7
status 4-5
subsystem ID 4-12
subsystem vendor ID 4-12
system doorbell 4-30
test base address 4-33
vendor ID 4-3
write sequence 4-30
register map A-1
PCI configuration space 4-2
PCI I/O space 4-29
reliability 1-13
reply FIFO register 4-37
reply free FIFO 2-7
reply interrupt 2-16
reply interrupt bit 4-35
reply interrupt mask bit 4-36
reply message 2-5 , 2-7 , 2-15 , 4-37
reply message queue 2-7
reply MFA 4-37
reply post FIFO 2-7 , 4-35