Avago Technologies LSI53C1030 - Manual (Page 48)

2-18 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
removes power from the LSI53C1030. D3
cold
can transition to D0 by
applying VCC and resetting the device.
Placing a function in Power State D3 puts the LSI53C1030 core in the
coma mode, clears the function's PCI
Command register, and continually
asserts the function's soft reset. Asserting soft reset clears all pending
interrupts and 3-states the SCSI bus.
2.4 Ultra320 SCSI Functional Description
The LSI53C1030 provides two independent Ultra320 SCSI channels on
a single chip. Each channel supports wide SCSI synchronous transfer
rates up to 320 Mbytes/s across an SE or LVD SCSI bus. The integrated
LVDlink transceivers support both LVD and SE signals and do not require
external transceivers. The LSI53C1030 controller supports the Ultra320
SCSI, Ultra160 SCSI, Ultra2 SCSI, Ultra SCSI, and Fast SCSI interfaces.
2.4.1 Ultra320 SCSI Features
This section describes how the LSI53C1030 implements the features in
the SPI-4 draft specification.
2.4.1.1 Parallel Protocol Request (PPR)
A SCSI extended message negotiates the PPR parameters. The PPR
parameters include the (1) transfer period, (2) maximum REQ/ACK
offset, (3) QAS, (4) margin control settings (MCS), (5) transfer width,
(6) IU_Request, (7) write flow, (8) read streaming, (9) RTI,
(10) precompensation enable, (11) information unit transfers, and the
(12) DT data phases between an initiator and a target.
2.4.1.2 Double Transition (DT) Clocking
Ultra160 SCSI and Ultra320 SCSI implement DT clocking to provide
speeds up to 80 megatransfers per second (megatransfers/s) for
Ultra160 SCSI, and up to 160 megatransfers/s for Ultra320 SCSI. When
implementing DT clocking, a SCSI device samples data on both the
asserting and deasserting edge of REQ/ACK. DT clocking is only valid
using an LVD SCSI bus.