Avago Technologies LSI53C1030 - Manual (Page 46)

2-16 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
implements its own MSI register set. The LSI53C1030 supports one
requested message and disables MSI after the chip powers-up or resets.
The Host Interrupt Mask register also prevents the assertion of a PCI
interrupt to the host processor by selectively masking reply interrupts and
system doorbell interrupts. This register masks both pin-based and MSI-
based interrupts.
2.3.6 Power Management
The LSI53C1030 complies with the PCI Power Management Interface
Specification, Revision 1.1, and the PC2001 System Design Guide. The
LSI53C01030 supports the D0, D1, D2, D3
hot
, and D3
cold
power states.
D0 is the maximum power state, and D3 is the minimum power state.
Power State D3 is further categorized as D3
hot
or D3
cold
. Powering a
function off places it in the D3
cold
Power State.
Bits [1:0] of the Power Management Control/Status register
independently control the power state of each PCI device on the
LSI53C1030.
Table 2.2 provides the power state bit settings.
The following sections describe the PCI Function Power States D0, D1,
D2, and D3. As the device transitions from one power level to a lower
one, the attributes that occur in the higher power state level carry into
the lower power state level. For example, Power State D2 includes the
attributes for Power State D1, as well as the attributes defined for Power
State D2. The following sections describe the PCI Function power states
in conjunction with each SCSI function. Power state actions are separate
for each SCSI function.
Table 2.2 Power States
Power Management Control and
Status Register, Bits [1:0] Power State Function
0b00 D0 Maximum Power
0b01 D1 Snooze Mode
0b10 D2 Coma Mode
0b11 D3 Minimum Power