Avago Technologies LSI53C1030 - Manual (Page 160)

IX-6 Index
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
message data register 4-23
message frame address 4-37
message passing technology 1-10 , 2-1
message queues 2-6 , 2-7
message signalled interrupts 2-15 , 2-16
message upper address register 4-23
MFA
reply 4-37
request 4-37
request free 4-37
minimum grant register 4-16
MOE/ 3-15 , 5-6
MSI 1-11 , 1-12 , 2-15 , 2-16 , 4-36
capability ID register 4-20
enable bit 4-22
message address 4-22
message data 4-23
message upper address register 4-23
multiple message 4-22
next pointer register 4-21
multifunction PCI 2-8 , 3-23 , 4-32
multi-ICE 2-30
multiple cache line transfers 2-14
multiple message capable 4-22
multiple message enable 4-21
N
NC 3-1 , 3-20
new capabilities bit 4-6
no connect 3-1
normal/fast memory (128 Kbytes)
single byte access read cycle 5-11 , 5-15
single byte access write cycle 5-13 , 5-16
NVSRAM 1-3 , 2-5 , 2-24 , 2-26 , 3-15
block diagram 2-27
integrated mirroring 2-26
interface 3-14
select 3-24
sense 3-22
write journaling 2-26
O
operating conditions 5-2
operating free air temperature 5-2
output signals 5-6
P
P1 line 2-19
paced transfers 1-2 , 2-19
package drawing 5-18 , 5-20
packetized protocol 1-2 , 1-10 , 2-21
packetized transfers 2-21
PAR 3-5 , 5-5
PAR64 3-5 , 5-5
parallel protocol request 2-18 , 2-22
parity error 4-6
passive termination 2-23
PC2001 system design guide 1-11 , 2-16
PCI 1-12 , 2-6
33 MHz 5-9
64-bit 3-21 , 3-22
66 MHz 3-21 , 3-22 , 5-9
66 MHz capable bit 4-6
address and data signals 3-5
address/data bus 3-21 , 4-27
addressing 2-8
alias to memory read block command 2-12 , 2-13
alias to memory write block command 2-12
arbitration 2-15
arbitration signals 3-7
benefits 1-6
bidirectional signals 5-5
bus commands 2-9 , 2-10
bus interface 3-4
cache line size register 2-14
cache mode 2-15
CLK 5-9
command 2-10
configuration read 2-8 , 2-10 , 2-12
configuration write 2-8 , 2-10 , 2-12
dual address cycle 2-13
dual address cycles 1-11 , 2-8
I/O read 2-10 , 2-11
I/O write 2-10
I/O write command 2-11
interrupt acknowledge 2-10
memory read 2-10
memory read block 1-11 , 2-10 , 2-12 , 2-14
memory read command 2-11
memory read dword 1-11 , 2-10
memory read dword command 2-11
memory read line 1-11 , 2-10 , 2-14
memory read multiple 1-11 , 2-10 , 2-13
memory write 2-10 , 2-11
memory write and invalidate 1-11 , 2-10 , 2-14
memory write block 1-11 , 2-10 , 2-15
memory write command 2-11
register 4-14
special cycle 2-10 , 2-11
split completion 1-11 , 2-10 , 2-13
command register 4-3
configuration read command 2-10 , 2-12 , 2-13 , 4-6
configuration record 2-28
configuration space 2-8 , 2-27 , 4-1
address map 4-2
C_BE[3:0]/ 2-8 , 2-9 , 2-10
configuration write command 2-10 , 2-12 , 2-13 , 4-6
DAC 1-11 , 2-8 , 2-10 , 2-13
device complexity bit 4-27