Avago Technologies LSI53C1030 - Manual (Page 47)

PCI Functional Description 2-17
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.3.6.1 Power State D0
Power State D0 is the maximum power state and is the power-up default
state for each function. The LSI53C1030 is fully functional in this state.
2.3.6.2 Power State D1
Per the PCI Power Management Interface Specification, Power State D1
must have an equal or lower power level than Power State D0. A function
in Power State D1 places the SCSI core in the snooze mode. In the
snooze mode, a SCSI reset does not generate an IRQ/ signal.
2.3.6.3 Power State D2
Per the PCI Power Management Interface Specification, Power State D2
must have an equal or lower power level than Power State D1. A function
in this state places the SCSI core in the coma mode. Placing the PCI
Function in Power State D2 disables the SCSI and DMA interrupts, and
suppresses the following PCI Configuration Space
Command register
enable bits:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR/Enable
•
Enable Parity Error Response
Therefore, the function's memory and I/O spaces cannot be accessed,
and the PCI function cannot be a PCI bus master.
If the PCI function is changed from Power State D2 to Power State D1
or D0, the PCI function restores the previous values of the PCI
Command register and asserts any interrupts that were pending before
the function entered Power State D2.
2.3.6.4 Power State D3
Per the PCI Power Management Interface Specification, Power State D3
must have an equal or lower power level than Power State D2. Power
State D3 is the minimum power state and includes the D3
hot
and D3
cold
settings. D3
hot
allows the device to transition to D0 using software. D3
cold