Avago Technologies LSI53C1030 User Manual
Page 113
PCI Configuration Space Register Description
4-27
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Designed Maximum Memory Read
Byte Count
[22:21]
These read only bits indicate a number greater than or
equal to the maximum byte count for the LSI53C1030
device. The PCI function uses this count to initiate a
sequence with one of the burst memory read commands.
The PCI function must report the smallest value that cor-
rectly indicates its capability. The LSI53C1030 reports
0b10 in this field to indicate that the designed maximum
memory read bytes count is 2048.
Device Complexity
20
The PCI function clears this read only bit to indicate that
the LSI53C1030 is a simple device.
Unexpected Split Completion
19
The PCI function sets this read only bit when it receives
an unexpected split completion. Once set, this bit
remains set until software clears it. Write a one (1) to this
bit to clear it.
Split Completion Discarded
18
The PCI function sets this read only bit when it discards
a split completion. Once set, this bit remains set until soft-
ware clears it. Write a one (1) to this bit to clear it.
133 MHz Capable
17
The MAD[15] Power-On Sense pin controls this read only
bit. Allowing the internal pull-downs to pull MAD[15] LOW
sets this bit and enables 133 MHz operation of the PCI
bus. Pulling MAD[15] HIGH clears this bit and disables
133 MHz operation of the PCI bus. Refer to
“Power-On Sense Pins Description,”
for more information
concerning the Power-On Sense pins.
64-bit Device
16
The MAD[14] Power-On Sense pin controls this read only
bit. Allowing the internal pull-downs to pull MAD[14] LOW
sets this bit and indicates a 64-bit PCI Address/Data bus.
Pulling MAD[14] HIGH clears this bit and indicates a
32-bit PCI Address/Data bus. If using the LSI53C1030 on
an add-in card, this bit must indicate the size of the card’s
PCI Address/Data bus. Refer to
for more information concerning
the Power-On Sense pins.