Table 4.9 interrupt signal routing, Interrupt signal routing, Host interrupt mask – Avago Technologies LSI53C1030 User Manual
Page 122: Host, Interrupt mask, Register: 0x34
4-36
PCI Host Register Description
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0x34
Host Interrupt Mask
Read/Write
The Host Interrupt Mask register masks and/or routes the interrupt
conditions that the
register reports. There is a
unique Host Interrupt Mask register for each PCI function.
Reserved
[
31:10]
This field is reserved.
Interrupt Request Routing Mode
[9:8]
This field routes PCI interrupts to the INTx/ or ALT_INTx/
pins according to the bit encodings in
. If the
host system enables MSI, the LSI53C1030 does not sig-
nal PCI interrupts on the INTx/ or ALT_INTx/ pins.
Reserved
[7:4]
This field is reserved.
Reply Interrupt Mask
3
Setting this bit masks reply interrupts and prevents the
assertion of a PCI interrupt for all reply interrupt condi-
tions.
Reserved
[2:1]
This field is reserved.
31
10 9
8
7
4
3
2
1
0
Host Interrupt Mask
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
1
X
X
1
Table 4.9
Interrupt Signal Routing
Bits [9:8] Encodings
Interrupt Signal Routing
0b00
INTx/ and ALT_INTx/
0b01
INTx/ only
0b10
ALT_INTx/ only
0b11
INTx/ only