Avago Technologies LSI53C1030 - Manual (Page 161)

Index IX-7
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
dual address cycles command 2-10 , 2-13
dual function 3-21
encoding 2-10
error reporting signals 3-7
frequency synthesizer 3-18 , 3-20 , 3-25
FSN 3-18 , 3-20 , 3-25
functional description 2-8
I/O read command 2-10 , 2-11 , 2-13
I/O space 2-8 , 2-9 , 4-1 , 4-28
I/O space address map 4-29
I/O space and memory space 4-28
I/O write command 2-10 , 2-11 , 2-13
interface 2-4
interface control signals 3-6
interrupt acknowledge command 2-10 , 2-13
interrupt signals 3-8
interrupts 2-15 , 4-36 , 4-37
memory [0] address map 4-29
memory [1] address map 4-29
memory read block command 2-13 , 2-14
memory read command 2-10 , 2-11 , 2-13 , 2-14 ,
2-15
memory read dword command 2-11 , 2-13
memory read line command 2-10 , 2-14 , 2-15
memory read multiple command 2-10 , 2-13 , 2-15
memory space 2-8 , 2-9 , 4-1
memory space [0] 2-4 , 2-9 , 2-27 , 4-1
memory space [1] 2-9 , 4-1
memory write and invalidate command 2-10 , 2-14 ,
2-15
memory write block command 2-12 , 2-15
memory write command 2-10 , 2-14 , 2-15
multifunction 2-8 , 4-32
new capabilities bit 4-6
performance 1-11
power management 2-16
power management interface specification 2-16
related signals 3-9
reset 4-32
single function 3-21 , 3-23
special cycle command 2-10 , 2-11 , 4-5
split completion command 2-13
status 3-22
system address space 4-1
system signals 3-4
PCI_CAP 3-22
PCI_GNT/ 3-16
PCI5VBIAS 1-12 , 3-20 , 5-5
PCI-SIG 4-12
PCI-X 1-11 , 1-12 , 2-8
133 MHz 3-21 , 5-9
133 MHz capable bit 4-27
64-bit device bit 4-27
66 MHz 5-9
alias to memory read block command 2-10
alias to memory write block command 2-10
benefits 1-6
bus commands 2-10
bus number 4-28
capability ID register 4-24
command register 4-24
commands 2-10
data parity error recovery enable bit 4-26
designed maximum cumulative read size bit 4-26
designed maximum memory read byte count bit 4-27
designed maximum outstanding split transactions bit
4-26
device complexity bit 4-27
device number bit 4-28
function number bit 4-28
maximum memory read byte count bits 4-25
maximum outstanding split transactions bits 4-24
memory read block command 2-10
memory read dword command 2-10
memory write block command 2-10
mode 3-21 , 3-22
next pointer register 4-24
received split completion error message bit 4-26
split completion command 2-10
split completion discarded bit 4-27
status 3-22
status register 4-26
unexpected split completion bit 4-27
PERR/ 3-7 , 5-5
pinout 5-22 , 5-24
PIPESTAT[2:0] 3-17 , 5-6
PME 4-18 , 4-19
clock bit 4-18
enable bit 4-19
status bit 4-19
support bits 4-18
POR 4-32
POST 4-15
power management 2-16
aux_current bit 4-18
bridge support extensions register 4-20
capabilities register 4-18
capability ID register 4-17
control/status register 2-16 , 4-19
D0 4-19
D1 4-19
D1 support bit 4-18
D2 4-19
D2 support bit 4-18
D3 2-17 , 4-19
data register 4-20