Avago Technologies LSI53C1030 - Manual (Page 13)

Contents xiii
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Tables
2.1 PCI/PCI-X Bus Commands and Encodings 2-10
2.2 Power States 2-16
2.3 Flash ROM Size Programming 2-24
2.4 Flash Signature Value 2-26
2.5 PCI Configuration Record in Serial EEPROM 2-28
2.6 20-Pin Multi-ICE Header Pinout 2-30
3.1 PCI System Signals 3-4
3.2 PCI Address and Data Signals 3-5
3.3 PCI Interface Control Signals 3-6
3.4 PCI Arbitration Signals 3-7
3.5 PCI Error Reporting Signals 3-7
3.6 PCI Interrupt Signals 3-8
3.7 PCI-Related Signals 3-9
3.8 SCSI Bus Clock Signal 3-10
3.9 SCSI Channel [0] Interface Signals 3-10
3.10 SCSI Channel [0] Control Signals 3-12
3.11 SCSI Channel [1] Interface Signals 3-13
3.12 SCSI Channel [1] Control Signals 3-14
3.13 Flash ROM/NVSRAM Interface Pins 3-14
3.14 Serial EEPROM Interface Pins 3-16
3.15 ZCR Configuration Pins 3-16
3.16 JTAG, ICE, and Debug Pins 3-17
3.17 LSI Logic Test Pins 3-18
3.18 GPIO and LED signals 3-19
3.19 Power and Ground Pins 3-20
3.20 MAD Power-On Sense Pin Options 3-21
3.21 PCI-X Function to SCSI Channel Configurations 3-24
3.22 Flash ROM Size Programming 3-24
3.23 Pull-Up and Pull-Down Conditions 3-25
4.1 LSI53C1030 PCI Configuration Space Address Map 4-2
4.2 Subsystem ID Register Download Conditions and Values 4-13
4.3 Multiple Message Enable Field Bit Encoding 4-22
4.4 Maximum Outstanding Split Transactions 4-25
4.5 Maximum Memory Read Count 4-25
4.6 PCI I/O Space Address Map 4-29
4.7 PCI Memory [0] Address Map 4-29