Avago Technologies LSI53C1030 - Manual (Page 164)

IX-10 Index
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
A_SD[15:0]+- 3-10
A_SDP[1:0]+- 3-10
A_SIO+- 3-12
A_SMSG+- 3-12
A_SREQ+- 3-12
A_SRST+- 3-12
A_SSEL+- 3-12
A_VDDBIAS 3-11
ACK64/ 3-6
AD[63:0] 3-5
ADSC/ 3-14
ADV/ 3-14
ALT_INTA/ 3-8 , 3-9
ALT_INTB/ 3-8 , 3-9
B_DIFFSENSE 3-13
B_LED/ 3-19
B_RBIAS 3-13
B_SACK+- 3-14
B_SATN+- 3-14
B_SBSY+- 3-14
B_SCD+- 3-14
B_SD[15:0]+- 3-13
B_SDP[1:0]+- 3-13
B_SIO+- 3-14
B_SMSG+- 3-14
B_SREQ+- 3-14
B_SRST+- 3-14
B_SSEL+- 3-14
B_VDDBIAS 3-13
BWE[1:0]/ 3-15
C_BE[7:0]/ 3-5
CLK 3-4
CLKMODE_0 3-18
CLKMODE_1 3-18
DEVSEL/ 3-6
DIS_PCI_FSN/ 3-18
DIS_SCSI_FSN/ 3-18
FLSHALE[1:0]/ 3-15
FLSHCE/ 3-15
FRAME/ 3-6
GNT/ 3-7
GPIO[7:0] 3-19
ground 3-20
HB_LED/ 3-19
IDDTN 3-18
IDSEL 3-6
INTA/ 3-8
INTB/ 3-8
IOPD_GNT/ 3-16
IRDY/ 3-6
MAD[15:0] 3-15 , 3-21
MADP[1:0] 3-15 , 3-21
MCLK 3-14
MOE/ 3-15
NC 3-20
PAR 3-5
PAR64 3-5
PCI5VBIAS 3-20
PERR/ 3-7
PIPESTAT[2:0] 3-17
power 3-20
power-on sense 3-21
PVT1,PVT2 3-9
RAMCE/ 3-15
REQ/ 3-7
REQ64/ 3-6
RST/ 3-4
RTCK_ICE 3-17
SCANEN 3-18
SCANMODE 3-18
SCLK 3-10
SerialCLK 3-16
SerialDATA 3-16
SERR/ 3-7
STOP/ 3-6
TCK_CHIP 3-17
TCK_ICE 3-17
TDI_CHIP 3-17
TDI_ICE 3-17
TDO_CHIP 3-17
TDO_ICE 3-17
TESTACLK 3-18
TESTCLKEN 3-18
TESTHCLK 3-18
TMS_CHIP 3-17
TMS_ICE 3-17
TN 3-18
TRACECLK 3-17
TRACEPKT[7:0] 3-17
TRACESYNC 3-17
TRDY/ 3-6
TRST_ICE/ 3-17
TST_RST/ 3-17
VDD_IO 3-20
VDDA 3-20
VDDC 3-20
VSS_IO 3-20
VSSA 3-20
VSSC 3-20
ZCR_EN/ 3-16
signal drive strength 2-20 , 2-22
signal list 5-22 , 5-24
signalled system error bit 4-5
signals
bidirectional 5-5
debug 3-17