Avago Technologies LSI53C1030 - Manual (Page 60)

2-30 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.8 Multi-ICE Test Interface
This section describes the LSI Logic requirements for the Multi-ICE test
interface. LSI Logic recommends that all test signals be routed to a
header on the board.
The Multi-ICE test interface header is a 20-pin header for Multi-ICE
debugging through the ICE JTAG port. This header is essential for
debugging both the firmware and the design functionality and must be
included in board designs. The connector is a 20-pin header that mates
with the IDC sockets mounted on a ribbon cable.
Table 2.6 details the
pinout of the 20 pin header.
Table 2.6 20-Pin Multi-ICE Header Pinout
Pin Number Signal Pin Number Signal
1 VDD 2 VDD
3 TRST_ICE/
1
1. The designer must connect a 4.7 k
Ω
resistor from this signal to 3.3 V.
4 VSS
5 TDI_ICE
1
6 VSS
7 TMS_ICE
1
8 VSS
9 TCK_ICE
1
10 VSS
11 RTCK_ICE 12 VSS
13 TDO_ICE 14 VSS
15 No Connect 16 VSS
17 No Connect 18 VSS
19 No Connect 20 VSS