Avago Technologies LSI53C1030 - Manual (Page 118)

4-32 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
writes a value other than the Write I/O Key to the Write
Sequence register.
Flash Bad Signature 6
The LSI53C1030 sets this bit if the IOP ARM966E-S pro-
cessor encounters a bad Flash signature when booting
from Flash ROM. The LSI53C1030 also sets the DisARM
bit (bit 1 in this register) to hold the IOP ARM processor
in a reset state. The LSI53C1030 maintains this state
until the PCI host clears both the Flash Bad Signature
and DisARM bits.
Reset History 5
The LSI53C1030 sets this bit if it experiences a Power
On Reset (POR), PCI Reset, or TestReset/. A host driver
can clear this bit to help coordinate recovery between
multiple driver instances in a multifunction PCI implemen-
tation.
Diagnostic Read/Write Enable 4
Setting this bit enables access to the Diagnostic
Read/Write Data and Diagnostic Read/Write Address
registers.
TTL Interrupt 3
Setting this bit configures PCI INTA/ as a TTL output.
Clearing this bit configures PCI INTA/ as an open-drain
output. Use this bit for test purposes only.
Reset Adapter 2
Setting this write only bit causes a hard reset within the
LSI53C1030. The bit self-clears after eight PCI clock peri-
ods. After deasserting this bit, the IOP ARM processor
executes from its default reset vector.
DisARM 1
Setting this bit disables the ARM processor.
Diagnostic Memory Enable 0
Setting this bit enables diagnostic memory accesses
through PCI Memory Space [1]. Clearing this bit disables
diagnostic memory accesses to PCI Memory Space [1]
and returns 0xFFFF on reads.