Avago Technologies LSI53C1030 - Manual (Page 103)

PCI Configuration Space Register Description 4-17
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0x3F
Maximum Latency
Read Only
Max_Lat [7:0]
This register specifies the desired settings for the latency
timer values in units of 0.25
µ
s. Max_Lat specifies how
often the device needs to gain access to the PCI bus.
The LSI53C1030 SCSI function sets this register to 0x06
since it requires the PCI bus every 1.5
µ
s to maintain a
data transfer rate of 320 Mbytes/s.
Register: 0xXX
Power Management Capability ID
Read Only
Power Management Capability ID [7:0]
This register indicates the type of the current data struc-
ture. It is set to 0x01 to indicate the Power Management
Data Structure.
Register: 0xXX
Power Management Next Pointer
Read Only
Power Management Next Pointer [7:0]
This register contains the pointer to the next item in the
PCI function’s extended capabilities list. The value of this
register varies according to system configuration.
7 0
Maximum Latency
0 0 0 0 0 1 1 0
7 0
Power Management Capability ID
0 0 0 0 0 0 0 1
7 0
Power Management Next Pointer
X X X X X X X X