Avago Technologies LSI53C1030 - Manual (Page 132)

5-8 Specifications
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.3 Rise and Fall Time Test Condition
I
LH
Input high leakage – 20
µ
A
−
0.5
DD
<5.25
V
PIN
= 2.7 V
I
LL
Input low leakage – 20
µ
A
−
0.5
DD
<5.25
V
PIN
= 0.5 V
R
I
Input resistance 20 – M
Ω
Receivers disabled
C
P
Capacitance per pin – 8 pF PQFP
dV
H
/dt Slew rate LOW to HIGH 110 540 mV/ns Figure 5.3
dV
L
/dt Slew rate HIGH to LOW 110 540 mV/ns Figure 5.3
ESD
HBM
Electrostatic discharge (HBM) 2 – kV MIL-STD-883C;
Method 3015-7;
100 pF at 1.5 k
Ω
ESD
CDM
Electrostatic discharge (CDM) 0.5 – kV ESD DS5.3.1-1996
Latch-up 100 – mA –
Filter delay 20 30 ns Figure 5.4
Ultra filter delay 10 15 ns Figure 5.4
Ultra2 filter delay 5 8 ns Figure 5.4
Extended filter delay 40 60 ns Figure 5.4
1. These values are guaranteed by periodic characterization; they are not 100% tested on every
device.
2. Active negation outputs only: Data, Parity, SREQ/, and SACK/. SCSI SE mode only (minus pins).
3. Single pin only; irreversible damage can occur if sustained for longer than one second.
Table 5.12 TolerANT Technology Electrical Characteristics for SE SCSI
Signals
1
(Cont.)
Symbol Parameter Min Max Units Test Conditions
+
-
2.5 V
47
Ω
20 pF