Avago Technologies LSI53C1030 - Manual (Page 139)

External Memory Timing Diagrams 5-15
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
5.4.2 Flash ROM Timing
Table 5.18 and Figure 5.10 provide the timing information for Flash ROM
read accesses.
Figure 5.10 Flash ROM Read Cycle
Table 5.18 Flash ROM Read Cycle Timing
Symbol Parameter Min Max Unit
t
1
Address setup to FLSHALE/ HIGH 25 – ns
t
2
Address hold from FLSHALE/ HIGH 25 – ns
t
3
FLSHALE/ pulse width 25 – ns
t
4
Address valid to data clocked in 135 – ns
t
5
FLSHCE/ LOW to data clocked in 85 – ns
t
6
MOE/ LOW to data clocked in 75 – ns
t
7
Data setup to MOE/ HIGH 10 – ns
t
8
Data setup to FLSHCE/ HIGH 10 – ns
t
9
Data hold from FLSHCE/ HIGH 0 – ns
Data driven by Flash)
MAD Bus
(Addr driven by LSI53C1030;
High Order
Address
Middle Order
Address
FLSHALE1/
(Driven by LSI53C1030)
FLSHALE0/
(Driven by LSI53C1030)
FLSHCE/
(Driven by LSI53C1030)
MOE/
(Driven by LSI53C1030)
BWE0/
(Driven by LSI53C1030)
t
3
t
1
t
2
t
4
t
5
t
6
Low Order
Address