Avago Technologies LSI53C1030 User Manual
Page 35
Block Diagram Description
2-5
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.1.1.5 Shared RAM
The host interface module physically contains the 96 Kbyte shared RAM.
However, both the host interface module and the SCSI channel modules
access the shared RAM. The shared RAM holds a portion of the IOP and
context manager firmware, as well as the request message queue and
reply message queue. All non-DMA data transfers that use the request
and reply message queues pass through the shared RAM.
2.1.1.6 External Memory Controller
The external memory control subsystem provides a direct interface
between the primary bus and the external memory subsystem. MAD[7:0]
and MADP[0] comprise the external memory bus. The LSI53C1030
supports the Flash ROM and NVSRAM interfaces through the external
memory controller. The Flash ROM is optional if the LSI53C1030 is not
the boot device and a suitable driver exists to initialize the device. The
LSI53C1030 uses the NVSRAM for write journaling when an Integrated
Mirroring (IM) volume is defined. Write journaling is used to verify that
the mirrored disks in the IM volume are synchronized with each other.
For a detailed description of this block refer to
During power up or reset the LSI53C1030 uses the MAD[15:0] and
MADP[1:0] signals as Power-On Sense pins, which configure the
LSI53C1030 through their pull-up or pull-down settings. Refer to
Section 3.10, “Power-On Sense Pins Description,”
for a description of the
Power-On Sense pin configuration options.
2.1.1.7 Timer, GPIO, and Configuration
This subsystem provides a free running timer to allow event time
stamping and also controls the general purpose I/O (GPIO), LED, and
serial EEPROM interfaces. The LSI53C1030 uses the free running timer
to aid in tracking and managing SCSI I/Os. The LSI53C1030 generates
the free running timer’s microsecond time base by dividing the SCSI
reference clock by 40.
The LSI53C1030 provides eight GPIO pins (GPIO[7:0]). These pins are
under the control of the LSI53C1030 and default to the input mode upon
PCI reset. The LSI53C1030 also provides three LED pins: A_LED/,
B_LED/, and HB_LED/. Either firmware or hardware control A_LED/ and