Avago Technologies LSI53C1030 - Manual (Page 38)

2-8 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.3 PCI Functional Description
The host PCI interface complies with the PCI Local Bus Specification,
Revision 2.2, and the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0a. The LSI53C1030 supports up to a 133 MHz,
64-bit PCI-X bus. The LSI53C1030 provides support for 64-bit
addressing with Dual Address Cycle (DAC).
The LSI53C1030 is a true multifunction PCI-X device and presents a
single electrical load to the PCI bus. The LSI53C1030 uses a single
REQ/-GNT/ pair to arbitrate for PCI bus mastership. Separate interrupt
signals for PCI Function [0] and PCI Function [1] allow independent
control of the two PCI functions.
2.3.1 PCI Addressing
The three physical address spaces the PCI specification defines are:
•
PCI Configuration Space
•
PCI I/O Space for operating registers
•
PCI Memory Space for operating registers
The following sections describe the PCI address spaces.
2.3.1.1 PCI Configuration Space
The LSI53C1030 defines an independent set of PCI Configuration Space
registers for each PCI function. Each configuration space is a contiguous
256 x 8-bit set of addresses. The system BIOS initializes the
configuration registers using PCI configuration cycles. The LSI53C1030
decodes C_BE[3:0]/ to determine if a PCI cycle intends to access the
configuration register space. The IDSEL signal behaves as a chip select
signal that enables access to the configuration register space only. The
LSI53C1030 ignores configuration read/write cycles when IDSEL is not
asserted.
Since the LSI53C1030 is a multifunction PCI device, bits AD[10:8]
decode either the PCI Function [0] Configuration Space (AD[10:8] =
0b000) or the PCI Function [1] Configuration Space (AD[10:8] = 0b001).
The LSI53C1030 does not respond to any other encodings of AD[10:8].