Avago Technologies LSI53C1030 User Manual
Page 163
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Index
IX-9
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
reply queue
REQ/
,
REQ/ACK offset,
REQ64/
request
request FIFO register
request free MFA
request message
request message frames
request message queue
request messages
request MFA
request post FIFO
request post MFA
requester ID
reset adapter bit
reset history bit
,
reset input
revision ID register
rise and fall time test condition
ROM
ROM expansion enable bit
ROM size
,
RST/
,
RTCK_ICE
,
RTI
RTI bit
S
SACK+-
SATN+-
SBSY+-
SCANEN
,
,
SCANMODE
,
SCD+-
SCLK
,
SCSI
A_DIFFSENS signal
B_DIFFSENS signal
bus interface
bus mastering functions
channel [0] interface
channel [1] interface
channel module
,
CLK
clock
core
CRC
datapath engine
domain validation
driver signals
DT clocking
dual channel
functions
information unit transfers
input filtering
interface signals
interrupt steering logic
ISI
LVD
paced transfers
packetized transfers
parallel protocol request
performance
PPR
precompensation
QAS
quick arbitration and selection
receiver signals
SE
single channel
single ended
skew compensation
synchronous transfer
termination
TolerANT technology
Ultra320 features
SD[15:0]+-
SDP[1:0]+-
SE
,
sense voltage
sense voltage
serial EEPROM
,
,
,
configuration record
download enable
,
interface
SerialCLK
,
SerialDATA
,
,
SERR/
,
,
SERR/ enable bit
shared RAM
signal
grouping
list
no connect
types
signal descriptions
A_DIFFSENS
A_LED/
A_RBIAS
A_SACK+-
A_SATN+-
A_SBSY+-
A_SCD+-